Example embodiments relate to semiconductor devices and, more particularly, to semiconductor devices that include low resistance buried gate structures and to related methods of manufacturing such devices,
As semiconductor devices become more highly integrated, the size of each unit cell of the devices and the widths of the patterns is decreased. Moreover, while the size of each unit cell is decreased, the electrical characteristics of the device typically must be maintained or improved. Accordingly, the integration density is often increased by stacking elements vertically relative to a substrate. For example, a transistor including a buried gate electrode has been developed that may exhibit both enhanced electrical characteristics and a high degree of integration.
Generally, the conventional buried gate structure is formed in a recess that is provided on a substrate. The conventional buried gate structure includes a gate dielectric layer pattern, a metal barrier layer pattern, a gate electrode and a gate mask. The gate dielectric layer pattern is formed on a bottom and a sidewall of the recess. The metal barrier layer pattern and the gate electrode are formed on the gate dielectric layer pattern. Each of the metal barrier layer pattern and the gate electrode has a height that is smaller than a height of the gate dielectric layer pattern. The gate mask is located on the metal barrier layer pattern and the gate electrode to fill the recess.
In the conventional buried gate structure, the gate electrode may not be properly formed on the metal barrier layer pattern, and the gate electrode may not have a low resistance when the gate electrode is directly formed on the metal barrier layer pattern. When the gate electrode includes tungsten (W), the gate electrode formed on the metal barrier layer pattern may have an α crystalline phase that has a resistance that is smaller than a resistance of a β crystalline phase. When the gate electrode includes tungsten of the β crystalline phase, the gate electrode may have a relatively large specific resistance, and thus the buried gate structure may also have an increased resistance. If the buried gate structure has a large resistance, the semiconductor device may have poor electrical characteristics. This may cause a number of problems, particularly with respect to semiconductor devices that have a design rule below about 20 nm.